<?xml version="1.0" encoding="UTF-8"?>
<RadiantProject version="4.2" radiant="2025.1.0.39.0" title="LED" device="LAV-AT-E70-3LFG1156C" performance_grade="3" family_int="ap6a00b" device_int="ap6a400cee" package_int="LFG1156" operation_int="COM" speed_int="3" default_implementation="impl_1">
    <Options/>
    <Implementation title="impl_1" dir="impl_1" description="impl_1" synthesis="synplify" default_strategy="Strategy1">
        <Options def_top="led"/>
        <Source name="../Led.v" type="Verilog" type_short="Verilog">
            <Options top_module="led"/>
        </Source>
        <Source name="led.pdc" type="Physical Constraints File" type_short="PDC">
            <Options/>
        </Source>
        <Source name="source/impl_1.xcf" type="Programming Project File" type_short="Programming">
            <Options/>
        </Source>
    </Implementation>
    <Strategy name="Strategy1" file="LED1.sty"/>
</RadiantProject>
